Quantum Optimization for FPGA Placement

Field-Programmable Gate Arrays (FPGAs) have become indispensable components in modern computing, providing adaptable and reconfigurable hardware platforms. FPGA-based accelerators offer promising avenues for advancements in diverse fields such as real-time data processing, machine learning, and cryptography. However, optimizing the spatial arrangement of functional blocks on an FPGA, known as placement, presents a challenging task due to its NP-hard nature, necessitating sophisticated algorithms for efficient solutions. Enhancing the placement process directly translates to reduced resource utilization during implementation. Quantum computing (QC) presents a promising approach for tackling such combinatorial problems by exploring vast solution spaces. In this paper, we propose a novel approach to the placement problem, re-formulating it as a series of quadratic unconstrained binary optimization (QUBO) problems, which we then solve using QC. Our novel formulation allows for straightforward integration of design constraints and enables the adaptation of sub-problem sizes to match hardware capabilities. Alongside presenting our method, we also investigate the resilience of contemporary quantum hardware in finding placements for real-world-sized FPGAs. A numerical assessment conducted on a D-Wave Advantage 5.4 quantum annealer indicates that the answer is indeed positive.