FPGA-Placement via Quantum Annealing

Field-Programmable Gate Arrays (FPGAs) have asserted themselves as vital assets in contemporary computing by offering adaptable, reconfigurable hardware platforms. FPGA-based accelerators incubate opportunities for breakthroughs in areas, such as real-time data processing, machine learning or cryptography — to mention just a few. The procedure of placement — determining the optimal spatial arrangement of functional blocks on an FPGA to minimize communication delays and enhance performance — is an NP-hard problem, notably requiring sophisticated algorithms for proficient solutions. Clearly, improving the placement leads to a decreased resource utilization during the implementation phase. Adiabatic quantum computing (AQC), with its capability to traverse expansive solution spaces, has potential for addressing such combinatorial problems. In this paper, we re-formulate the placement problem as a series of so called quadratic unconstrained binary optimization (QUBO) problems which are subsequently solved via AQC. Our novel formulation facilitates a straight-forward integration of design constraints. Moreover, the size of the sub-problems can be conveniently adapted to the available hardware capabilities. Beside the sole proposal of a novel method, we ask whether contemporary quantum hardware is resilient enough to find placements for real-world-sized FPGAs. A numerical evaluation on a D-Wave Advantage 5.4 quantum annealer suggests that the answer is in the affirmative.